Simulation of Vending Machine Design using Verilog HDL
Rishabh Sati, Varun Mishra, Gourav Verma
Abstract
Today, due to advancement in the field of electronic industry vending machine use is increasing rapidly. Food items, newspaper, beverages, Toys, tickets, and lot more consumer products are sold. Due to better quality product and fast processing speed users of vending machines are increasing in metropolitan cities. This paper aims to design an FSM based vending machine for dispensing products of different types and cost and verify its behavioral specification, logical operation and to generate RTL netlist of the proposed design. The proposed algorithm is implemented using Verilog HDL in Xilinx Vivado 2018.3 tool and simulated using Vivado simulator.
Topics & Concepts
VerilogNetlistComputer scienceEmbedded systemProduct (mathematics)Field-programmable gate arrayComputer architectureMathematicsGeometryLow-power high-performance VLSI designNumerical Methods and AlgorithmsVLSI and FPGA Design Techniques