Advanced 2T0C DRAM Technologies for Processing-in-Memory—Part I: Vertical Transistor on Gate (VTG) DRAM Cell Structure
Siyuan Kong, Wonbo Shim
Abstract
Two-transistor-zero-capacitor (2T0C) DRAM cell has been proposed and extensively investigated as a memory device for processing-in-memory (PIM) applications. In this two-part article, we propose a novel vertical-transistor on gate (VTG) 2T0C DRAM cell structure and the refresh technique for PIM applications and demonstrate their effectiveness. Due to its volatile characteristics and capacitorless structure, conventional logic compatible 2T0C DRAM-based PIM experiences a decline in inference accuracy. As a result, the frequent refresh operations are inevitable to achieve acceptable inference accuracy, which may result in significant energy consumption. In this article, we proposed and modeled the unit cell of VTG 2T0C DRAM using TCAD simulation and described the device characterization. Compared to a planar-only 2T0C DRAM with 65-nm process, the VTG DRAM cell structure achieved an improvement of approximately 567% in retention characteristics. The inference accuracy and the hardware performance of the VTG DRAM-based PIM macro will be described in Part II of this article.