Engineering of Grain Boundaries in CeO<sub>2</sub> Enabling Tailorable Resistive Switching Properties
Hongyi Dou, Markus Hellenbrand, Ming Xiao, Zedong Hu, Sundar Kunwar, Aiping Chen, Judith L. MacManus‐Driscoll, Q. X. Jia, Haiyan Wang
Abstract
Abstract Defect engineering in valence change memories aimed at tuning the concentration and transport of oxygen vacancies are studied extensively, however mostly focusing on contribution from individual extended defects such as single dislocations and grain boundaries. In this work, the impact of engineering large numbers of grain boundaries on resistive switching mechanisms and performances is investigated. Three different grain morphologies, that is, “random network,” “columnar scaffold,” and “island‐like,” are realized in CeO 2 thin films. The devices with the three grain morphologies demonstrate vastly different resistive switching behaviors. The best overall resistive switching performance is shown in the devices with “columnar scaffold” morphology, where the vertical grain boundaries extending through the film facilitate the generation of oxygen vacancies as well as their migration under external bias. The observation of both interfacial and filamentary switching modes only in the devices with a “columnar scaffold” morphology further confirms the contribution from grain boundaries. In contrast, the “random network” or “island‐like” structures result in excessive or insufficient oxygen vacancy concentration migration paths. The research provides design guidelines for grain boundary engineering of oxide‐based resistive switching materials to tune the resistive switching performances for memory and neuromorphic computing applications.