UC-Check: Characterizing Micro-operation Caches in x86 Processors and Implications in Security and Performance
Joonsung Kim, Hamin Jang, Hunjun Lee, Seung‐Ho Lee, Jangwoo Kim
Abstract
The modern x86 processor (e.g., Intel, AMD) translates CISC-style x86 instructions to RISC-style micro operations (uops) as RISC pipelines are more efficient than CISC pipelines. However, this x86 decoding process requires complex hardware logic (i.e., x86 decoder) to identify variable-length x86 instructions, which incurs high translation overhead. To avoid this overhead, the x86 processors adopt a micro-operation cache (uop cache) to bypass the expensive x86 decoder by caching the decoded uops.
Topics & Concepts
x86Computer scienceCacheOverhead (engineering)Embedded systemReduced instruction set computingBootingParallel computingOperating systemInstruction setSoftwareSecurity and Verification in ComputingParallel Computing and Optimization TechniquesPhysical Unclonable Functions (PUFs) and Hardware Security