Anomalous Behavior of Gate Current and TDDB Lifetime by Constant Voltage Stress in NO-Annealed SiC-MOSFETs
Eiichi Murakami, Mitsuo Okamoto
Abstract
Silicon-carbide metal-oxide-semiconductor field-effect transistors (SiC-MOSFETs) are core devices for future power electronics. The factors limiting their automotive applications are currently under investigation. Postoxidation annealing in NO gas is a key technology to achieving high carrier mobility in SiC-MOSFETs. In this article, we study the NO annealing effects on time-dependent dielectric breakdown (TDDB) reliability by the constant voltage stress (CVS) method at room temperature (RT). We show that heavy NO annealing enhances hole trapping near the SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /SiC interface and leads to a rapid increase in the gate current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> ) and results in shorter time-to-breakdown (t <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BD</sub> ) and smaller Weibull slope of t <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BD</sub> in comparison to light NO annealing case. However, the detailed examination of the I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> behavior reveals that the charge-to-breakdown (Q <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BD</sub> ) and its distribution do not deteriorate. Therefore, we must reconsider the use of the CVS method by examining the I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> behavior during stress, which strongly depends on NO annealing conditions.