A 5.6-89.9TOPS/W Heterogeneous Computing-in-Memory SoC with High-Utilization Producer-Consumer Architecture and High-Frequency Read-Free CIM Macro
Jinshan Yue, Mingtao Zhan, Zi Wang, Yifan He, Yaolei Li, Songming Yu, Wenyu Sun, Lu Jie, Chunmeng Dou, Xueqing Li, Nan Sun, Huazhong Yang, Ming Liu, Yongpan Liu
Abstract
This work presents an energy-efficient CIM SoC with heterogeneous CPU, CIM, SIMD, DMA and COMM cores. The main contributions include: 1) A producer-consumer instruction dependency controller (PCIDC) with shared multi-port SRAM to reduce CIM SoC-level data transfer. 2) An inner-pipelined read-free digital CIM macro to achieve higher frequency. 3) A parallel-to-serial (PTS) sparse architecture utilizing the low activity of partial-sum accumulation. This work demonstrates the first digital-CIM SoC. The fabricated 55nm chip achieves 261TOPS/W (macro) and 33.0TOPS/W (SoC) end-to-end energy efficiency on the test models. The peak SoC energy efficiency is 3.03× higher than the state-of-the-art analog-CIM SoC.