A 128-kbit GC-eDRAM With Negative Boosted Bootstrap Driver for 11.3× Lower-Refresh Frequency at a 2.5% Area Overhead in 28-nm FD-SOI
H. Andac Yigit, Emmanuel Nieto Casarrubias, Robert Giterman, Andreas Burg
Abstract
Gain-cell embedded DRAM (GC-eDRAM) is a high-density logic-compatible alternative to conventional static random-access memory (SRAM) and embedded DRAM (eDRAM). However, GC-eDRAM suffers from a reduced data retention time (DRT) at deeply-scaled process nodes, leading to frequent power-hungry refresh operations. In order to reduce the refresh overhead, GC-eDRAM macros utilize external assist voltages which improve the bitcell write-ability, leading to an enhanced DRT. However, the requirement for external analog supply voltages creates additional overhead and is often impractical in the design of compact systems-on-chip (SoC). This work presents an on-chip write-assist technique implemented with a negative boosted bootstrap driver which generates the required wordline boosting on-chip without external components. The proposed circuitry is integrated compactly inside the GC-eDRAM macro to provide an area-efficient low-power solution which improves the bitcell’s write-ability and reduces its refresh requirement. A 128-kbit GC-eDRAM macro utilizing the proposed boosting circuitry has been fabricated in a 28-nm FD-SOI technology, demonstrating an <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$11.3\times $ </tex-math></inline-formula> DRT improvement at only 2.5% area overhead.