Numerical and Experimental Studies of Fabrication-Induced Thermal Residual Stresses in Microelectronic Packages

Abstract

Microelectronic packages are typically composed of different layers of materials with un-similar thermo-mechanical properties. Fabrication-induced residual stresses, resulting from the mismatch of layers' thermo-mechanical properties, may lead to adverse effects such as warpage and delamination at the interface of layers. In this study, the fabrication process of the ball grid array (BGA) package was simulated to predict the thermal residual stresses through the thickness of the package. A finite-element model incorporating realistic material behavior of the BGA package layers was developed. To this end, the epoxy molding compound (EMC) was modeled as a viscoelastic material, while the silicon chip, the die-attach, and the composite substrate were simulated using an elastic model during cooling. Since Young's modulus of EMC is time and temperature-dependent, three different process temperatures were simulated to investigate the impact of viscoelastic properties of EMC, defined using Prony coefficients, on numerical residual stresses. To verify the simulation results, the incremental hole-drilling method was used to experimentally measure the residual stress components. It includes drilling a small hole at the center of a rosette strain gauge bonded on the BGA package surface and measuring the released strains on the surface. The relaxed strains were then converted to the residual stresses using a calibration matrix whose coefficients are determined from a finite-element model. The reasonable agreement of numerical and experimental components of the residual stress throughout the thickness of the BGA package confirms the reliability of the proposed simulation approach in estimating residual stresses in microelectronics packages.

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