A 0.003-mm2 440fsRMS-Jitter and −64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS

Zunsong Yang, Yong Chen, Pui‐In Mak, Rui P. Martins

2021IEEE Transactions on Circuits and Systems I Regular Papers25 citationsDOI

Abstract

This paper presents a linear current-reuse sampling phase detector for a single-loop type-I phase-locked loop (PLL) to simultaneously achieve a wide loop bandwidth and low control voltage ripple, resulting in low RMS jitter and reference spur, while minimizing the chip area by avoiding an explicit loop filter. Fabricated in 28-nm CMOS, the PLL prototype measures an integrated jitter of 440 fs RMS , and a spur level of -63.9 dBc at 3.296 GHz. It draws 3.3 mW at a 0.9-V supply and scores a jitter-power figure-of-merit (FoM) of -241.9 dB. With a 103-MHz reference input, a bandwidth of ~20 MHz aids suppressing significantly the ring VCO's phase noise (PN), leading to an in-band PN of -116 dBc/Hz at 1-MHz offset. The die size is 0.003 mm 2 .

Topics & Concepts

Voltage-controlled oscillatorPhase-locked loopJitterdBcPhase noiseCMOSPhysicsDetectorElectrical engineeringElectronic engineeringVoltageOptoelectronicsEngineeringAdvancements in PLL and VCO TechnologiesRadio Frequency Integrated Circuit DesignSemiconductor Lasers and Optical Devices

A 0.003-mm<sup>2</sup> 440fs<sub>RMS</sub>-Jitter and −64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS

Abstract

Topics & Concepts