Characterization and Analysis on Performance and Avalanche Reliability of SiC MOSFETs With Varied JFET Region Width
Zhengyun Zhu, Na Ren, Hongyi Xu, Li Liu, Kuang Sheng
Abstract
In this work, the influence of JFET region width on device's performance and avalanche reliability is studied on 1200 V planar-gate silicon carbide (SiC) MOSFETs fabricated on a 4-in SiC wafer. Unclamped inductive switching (UIS) test is conducted to compare the devices under tests (DUTs) avalanche capability at both V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> = 0 V and V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> = -5 V. At V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> = 0 V, the best avalanche reliability is achieved with a JFET region width of 4 μm. Through mix-mode TCAD simulation, channel conduction is found to contribute to the failure at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> = 0 V. While at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> = -5 V, the best avalanche reliability is achieved with a JFET region width ranging from 2 to 3 μm. Hole injection is observed in the test and recognized in simulation, which critically influences the DUTs' avalanche reliability at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> = -5 V.