Accurate timing prediction at placement stage with look-ahead RC network

Xu He, Zhiyong Fu, Yao Wang, Chang Liu, Yang Guo

2022Proceedings of the 59th ACM/IEEE Design Automation Conference42 citationsDOI

Abstract

Timing closure is a critical but effort-taking task in VLSI designs. In placement stage, a fast and accurate net delay estimator is highly desirable to guide the timing optimization prior to routing, and thus reduce the timing pessimism and shorten the design turn-around time. To handle the timing uncertainty at the placement stage, we propose a fast net delay timing predictor based on machine learning, which extract the fully timing features using a look-ahead RC network. Experimental results show that the proposed timing predictor has achieved average correlation over 0.99 with the post-routing sign-off timing results obtained in Synopsys PrimeTime.

Topics & Concepts

Static timing analysisComputer scienceEstimatorRouting (electronic design automation)Task (project management)Very-large-scale integrationElmore delayReal-time computingDelay calculationEmbedded systemPropagation delayEngineeringStatisticsMathematicsComputer networkSystems engineeringVLSI and Analog Circuit TestingVLSI and FPGA Design TechniquesLow-power high-performance VLSI design