A 50.1-Mpixel 14-Bit 250-frames/s Back-Illuminated Stacked CMOS Image Sensor With Column-Parallel <i>kT</i>/<i>C</i>-Canceling S&H and ΔΣADC
Chihiro Okada, Golan Zeituni, Koushi Uemura, Luong Dinh Hung, Kouji Matsuura, Takashi Moue, Kazutoshi Kodama, Masafumi Okano, Takafumi Morikawa, Kazuyoshi Yamashita, Osamu Oka, Yoshiaki Inada, Itai Shvartz, Ariel Ben Shem, Noam Eshel
Abstract
This article presents a 50.1-Mpixel 14-bit 250-frames/s back-illuminated stacked CMOS image sensor on 35-mm optical format exhibiting 1.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{e}^{-}$ </tex-math></inline-formula> rms random noise at 0 dB. This sensor employs a load reduction technique by splitting half of pixel signal line using a Cu-Cu connection technology underneath the pixel area, pipelined operation with a gain-adaptive column-parallel <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">kT</i> / <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$C$ </tex-math></inline-formula> noise-canceling sample and hold, and a 250-frames/s scanning rate and 14-bit resolution delta-sigma analog-to-digital converter (ADC) circuit. Moreover, an on-chip online calibration of column mismatch maintains the non-linearity of the output image within −0.42%. As a result, FoM6 ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{e}^\ast $ </tex-math></inline-formula> pJ/step) of 0.09 is obtained as the state-of-the-art performance.