Implementation of Wallace Tree Multiplier Using 8:4 Compressor
Kavinaath Murugan
2021Turkish Journal of Computer and Mathematics Education (TURCOMAT)24 citations
Abstract
Multipliers are prime scheme implementation of Microprocessors, VLSI and Embedded Systems. Regrettably, Multipliers are designate by compound function represent and constitute one of the supreme power consuming digital blocks. Estimate computing is an Emerging trend in VLSI design. Now a day the Multiplier is a vital role in most research and development areas. In this paper, the Implementation of Wallace tree Multiplier using 8:4 Compressor is done. The multiplier design will be made by 8:4 Compressor that reduces the power consumption than the optimized compressor design. The proposed 8:4 Compressor is implemented using AND and OR gates.
Topics & Concepts
Gas compressorMultiplier (economics)Very-large-scale integrationComputer scienceArithmeticPower consumptionBooth's multiplication algorithmComputer hardwareEmbedded systemPower (physics)MathematicsElectronic engineeringEngineeringAdderCMOSEconomicsQuantum mechanicsPhysicsMacroeconomicsMechanical engineeringLow-power high-performance VLSI designParallel Computing and Optimization TechniquesEmbedded Systems Design Techniques