Intermediate Layer‐Assisted Trap Density Reduction in Low‐Power Optoelectronic Memristors for Multifunctional Systems
Min Jong Lee, Tae Hyuk Kim, Sang Heon Lee, Seunghyun Oh, Muhammad Asghar Khan, Gyeong Min Lee, Young Kyun Choi, Soyeon Lee, Hyungju Ahn, Soong Ju Oh, Jiwoong Yang, Jae Won Shim
Abstract
Abstract The rapid expansion of the Internet of Things demands low‐power devices that integrate memory, sensors, and logic functions. Perovskite materials show promise for low‐power optoelectronic memristors; however, challenges such as nonuniform trap distribution and uncontrolled filament formation hinder their resistive switching performance. To overcome these issues, a TiO 2 nanofilm via atomic layer deposition as a base layer for filament formation, is introduced. This layer passivates interfacial defects by forming strong chemical interactions with Pb 2+ and I − ions at the perovskite interface, significantly reducing trap densities (interface trap density decreases 15‐fold to 3.0 × 10 16 cm −3 , and bulk trap density to 1.8 × 10 14 cm −3 ). Improved energy band alignment enables efficient electron transport, yielding a low‐ V SET (+0.24 V) and excellent low‐power (≈0.7 µW) nonvolatile memory performance. Additionally, the device reliably detects near‐infrared illumination as an optical input and enables reconfigurable image recognition using a 5 × 5 array under combined stimuli. It also facilitates the implementation of complex logic gates, such as AND, OR, and flip‐flops. This paper demonstrates the potential for integrating nonvolatile memory, sensing, and logic functionalities into a single low‐power device through the incorporation of a TiO 2 nanolayer.