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A 107.6 dB-DR Three-Step Incremental ADC for Motion-Tolerate Biopotential Signals Recording

Lairong Fang, Shuwen Zhang, Yijie Li, Shunmin Wu, Xiaoyang Zeng, Zhiliang Hong, Jiawei Xu

2023IEEE Transactions on Biomedical Circuits and Systems13 citationsDOI

Abstract

This article describes a power-efficient, high dynamic range (DR) incremental ADC (IADC) for wearable biopotential signals recording, where DC and low-frequency disturbances such as electrode offset, 50/60 Hz interference and motion artifact must be tolerated. To achieve a wide DR, the IADC performs a three-step conversion by combining zoom-SAR and extended counting (EC) on top of a second-order incremental delta-sigma modulator (ΔΣM). The hybrid architecture notably reduces the oversampling ratio (OSR) with respect to conventional incremental ΔΣMs, while using the EC further improves the Signal-to-Noise-and-Distortion Ratio (SNDR) by 7.4 to 25.6 dB. Fabricated in a 0.18-μm CMOS technology, the IADC achieves 107.6-dB DR, 104.9-dB peak SNR, and 99.3-dB peak SNDR at 2 kS/s while dissipating 130 μW from 1.8-V (analog) / 1.2-V (digital) supply. This translates to a highly competitive FoM<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DR</sub> of 176.5 dB. The high-DR IADC reduces the gain of the preceding instrumentation amplifier (IA) such that significant DC and low-frequency disturbances can be tolerated. The advantages of high DR have been demonstrated by wearable Electrocardiography (ECG) and Electroencephalography (EEG) recordings under motion artifact.

Topics & Concepts

OversamplingAmplifierDynamic rangeDelta-sigma modulationElectronic engineeringComputer scienceCMOSSignal-to-noise ratio (imaging)Noise (video)Electrical engineeringEngineeringArtificial intelligenceTelecommunicationsImage (mathematics)Analog and Mixed-Signal Circuit DesignECG Monitoring and AnalysisNeuroscience and Neural Engineering
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