Power-Efficient Secured Hardware Design of AES Algorithm on High Performance FPGA
Keshav Kumar, Vijay Singh, Gaurav Mishra, B. Ravindra Babu, Nandita Tripathi, P. Deepak Kumar
Abstract
With the expansion and growth of industries, the two major issues exist that affect both civilization and the environment. Technology development has made it more difficult to communicate and transmit data over secure channels. The use of Green Communication (GC) technology and energy-efficient parts can lessen the lack of electricity and energy. The usage of various technologies under one framework is the main topic of this study. In this article, a hardware implementation of the Advanced Encryption Standard (AES) algorithm is shown. Field Programmable Gate Array (FPGA) devices are taken into consideration for hardware implementations. The power calculation of the AES algorithm is computed for several clock speeds of the Spartan-7 FPGA, and the results are examined using VIVADO tool.