A fast locking and low jitter hybrid ADPLL architecture with bang bang PFD and PVT calibrated flash TDC
Jagdeep Kaur Sahani, Anil Singh, Alpana Agarwal
Topics & Concepts
JitterPhase-locked loopPhase noiseDigitally controlled oscillatorCMOSElectronic engineeringPhase detectorPhase frequency detectorTime-to-digital converterVoltageComputer scienceElectrical engineeringEngineeringCharge pumpCapacitorVariable-frequency oscillatorClock signalAdvancements in PLL and VCO TechnologiesOptical Network TechnologiesRadio Frequency Integrated Circuit Design