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32.4 A 104fs<sub>rms</sub>-Jitter and -61dBc-Fractional Spur 15GHz Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancelation Technique

Juyeop Kim, Yongwoo Jo, Younghyun Lim, Taeho Seong, Hangi Park, Seyeon Yoo, Yongsun Lee, Seojin Choi, Jaehyouk Choi

202129 citationsDOI

Abstract

Subsampling PLLs (SSPLLs) are attractive architectures to generate ultra-low-jitter RF signals due to their intrinsically high phase-error-detection gain, KSH. However, this high-gain operation of a sample-and-hold circuit (SH) also has a downside that makes it difficult to achieve a fractional resolution. This is because the quantization error (Q-error) due to the non-integer relationship between the reference frequency, fREF, and the VCO frequency, f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VCO</sub> , easily makes sampling points fall outside the linear range of the SH. Thus, to have a fractional resolution, SSPLLs must have a dedicated method for cancelling the Q-error. The top left of Fig. 32.4.1 shows a time-domain Q-error cancellation (TD-QEC) that is currently popular [1]. As a digital-to-time converter (DTC) cancels the Q-error, the VCO output, S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VCO</sub> , can be continuously sampled at high-K <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SH</sub> points in the steady state. However, a critical problem is that, since the DTC is located at the front, its thermal noise cannot be suppressed by K <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SH</sub> degrading the in-band phase noise (PN) of SSPLLs. In contrast, in reference-sampling PLLs (RSPLLs) [2,3], the divided signal of the S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VCO</sub> samples the reference clock, SREF. However, they have a fundamental limit to achieve a low jitter since their K <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SH</sub> is much smaller than that of SSPLLs while the thermal noise of the DTC is still high.

Topics & Concepts

Voltage-controlled oscillatorJitterQuantization (signal processing)AlgorithmPhase noisePhase-locked loopComputer scienceElectronic engineeringControl theory (sociology)Electrical engineeringVoltageArtificial intelligenceTelecommunicationsEngineeringControl (management)Advancements in PLL and VCO TechnologiesRadio Frequency Integrated Circuit DesignPhotonic and Optical Devices