An 8T PA Attack Resilient NVSRAM for In-Memory-Computing Applications
Sandeep Tripathi, Sudhanshu Choudhary, Prasanna Kumar Misra
Abstract
The proposed 8T Non-Volatile SRAM (NVSRAM) is designed to be resistant to power analysis (PA) attacks and is suitable for in-memory computing (IMC) applications. Our design uses a two-phase write operation instead of the traditional single-phase write operation, which reduces the correlation between stored data and power consumption during writing and provides resilience against PA attacks. It provides a mean energy difference (MED) of 5aJ, which is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1000\times $ </tex-math></inline-formula> less compared to available 6T SRAM cells. The proposed cell also utilizes a common Spin transfer torque (STT) current for both magnetic tunnel junctions (MTJs), which results in more energy efficient and faster store operations. The store operation becomes <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2\times $ </tex-math></inline-formula> more energy efficient and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3\times $ </tex-math></inline-formula> faster compared to the available state of the art NVSRAM Cells. The Symmetrical structure of proposed cell and two stage store/restore operation provide PA attack resiliency during store and restore mode of NVSRAM. Additionally, the proposed cell performs IMC for XNOR computation by collocating the weights and activations stored in the same bit cell.