Scaling up silicon photonic-based accelerators: Challenges and opportunities
Mohammed Al-Qadasi, Lukas Chrostowski, Bhavin J. Shastri, Sudip Shekhar
Abstract
Digital accelerators in the latest generation of complementary metal–oxide–semiconductor processes support, multiply, and accumulate (MAC) operations at energy efficiencies spanning 10–100 fJ/Op. However, the operating speed for such MAC operations is often limited to a few hundreds of MHz. Optical or optoelectronic MAC operations on today’s SOI-based silicon photonic integrated circuit platforms can be realized at a speed of tens of GHz, leading to much lower latency and higher throughput. In this Perspective, we study the energy efficiency of integrated silicon photonic MAC circuits based on Mach–Zehnder modulators and microring resonators. We describe the bounds on energy efficiency and scaling limits for N × N optical networks with today’s technology based on the optical and electrical link budget. We also describe research directions that can overcome the current limitations.