First Demonstration of GAA Monolayer-MoS<sub>2</sub> Nanosheet nFET with 410μA μ m ID 1V VD at 40nm gate length
Yun-Yan Chung, Bo-Jhih Chou, Chen-Feng Hsu, Wei‐Sheng Yun, Ming‐Yang Li, Sheng‐Kai Su, Yu-Tsung Liao, Meng-Chien Lee, Guo‐Wei Huang, San‐Lin Liew, Yun-Yang Shen, Wen‐Hao Chang, Chien-Wei Chen, Chi‐Chung Kei, Han Wang, H.‐S. Philip Wong, T. Y. Lee, Chao-Hsin Chien, Chao-Ching Cheng, Iuliana Radu
Abstract
This work demonstrates the first successful integration of monolayer MoS <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> nanosheet FET in a gate-all-around configuration. At a gate length of 40nm, the transistor exhibits a remarkable $\mathrm{I}_{\mathrm{ON}} \sim 410 \mu \mathrm{A}/ {\mu} \mathrm{m}$ at $\mathrm{V}_{\mathrm{DS}}=1\ \mathrm{V}$, achieved with a monolayer channel, ‘0.7 nm thin. The FET has a large $\mathrm{I}_{\mathrm{ON}}/ \mathrm{I}_{\mathrm{OFF}} \gt 1\mathrm{E}8$, positive $\mathrm{V}_{\mathrm{TH}} \sim 1.4\ \mathrm{V}$ with nearly zero DIBL. Higher drive current can be achieved through stacking of multiple channel layers. We propose here a fully integrated flow and we detail the feasibility of the most critical modules: stack/channel preparation, fin patterning, inner spacer, channel release, contact. The successful demonstration of MoS <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> NS with high performance and of the stacked NS modules further clarifies the value proposition in 2D materials for transistor scaling.