Incremental Drain-Voltage-Ramping Training Method for Ferroelectric Field-Effect Transistor Synaptic Devices
Manh-Cuong Nguyen, Kitae Lee, Sihyun Kim, Sangwook Youn, Yeongjin Hwang, Hyungjin Kim, Rino Choi, Daewoong Kwon
Abstract
We demonstrate a HfZrO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> (HZO) ferroelectric field-effect transistor fabricated on a silicon-on-insulator substrate, targeting MHz synaptic device applications. Stable multistate weights were implemented with robust retention, excellent linearity, and symmetric potentiation/depression (P/D) in the fabricated HZO ferroelectric field-effect transistors (FeFETs). To further improve the linearity and symmetry of the P/D and to expand the operating condition of the FeFETs as a synaptic device, a novel incremental drain-voltage-ramping method was proposed, and its compatibility was verified thoroughly. The results revealed that a linear and symmetric P/D with stable repeatability was obtained under a wide range of operating conditions, and a learning accuracy of 95% was achieved through MNIST pattern recognition simulations.