30.9 A 90<sub>%</sub>-Efficiency 40.68MHz Single-Stage Dual-Output Regulating Rectifier with ZVS and Synchronous PFM Control for Wireless Powering
Ziyang Luo, Jin Liu, Hoi Lee
Abstract
Wireless power transfer (WPT) is a common non-intrusive approach to power implantable biomedical devices. In the WPT system, a tens-of-milliwatt power receiver (RX) should offer a small form factor and is preferred to provide two or more power rails for supporting various functions. Conventionally, the power RX can be realized by a rectifier for the AC-to-DC conversion followed by a single-inductor multiple-output (SIMO) converter for generating different regulated DC voltages. Although rectifiers with a high resonance frequency <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\mathbf{f}_{\mathbf{R}\mathbf{E}\mathbf{S}})$</tex> of 40.68MHz were recently presented to reduce the required size of the off-chip RX coil [1], [2], the power receiver form factor and efficiency could suffer considerably due to the SIMO converter. For example, the receiver with a single-inductor dual-output converter [3] involving five off-chip components (1 inductor and 4 capacitors) to produce two outputs is sizable and its peak efficiency is only 80%. To simplify the structure of the power receiver, various single-stage dual-output regulating (SSDOR) rectifiers were reported [4–6]. While [4] can operate at <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{f}_{\text{RES}}$</tex> of 13.56MHz, the use of ten power transistors and realizing output regulation via switch on-resistance modulation limit its power efficiency. Although the dual-output generation in [5] only requires six power transistors, both output voltages must be very close to each other due to its architectural constraint, and it only operates at a low <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{f}_{\text{RES}}\text{of} \ 25\text{kHz}$</tex> . The SSDOR rectifier in [6] further reduces the number of power transistors to four and increases <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{f}_{\text{RES}}$</tex> to 6.78MHz, but it cannot be used in low-power parallel LC tank applications.