Gate-All-Around Strained Si<sub>0.4</sub>Ge<sub>0.6</sub> Nanosheet PMOS on Strain Relaxed Buffer for High Performance Low Power Logic Application
Ankur Agrawal, S. Chouksey, W. Rachmady, Suresh Vishwanath, Srabantika Ghose, M. Mehta, J. Torres, A. Oni, X. Weng, H. Li, Devin R. Merrill, M. Metz, A. Murthy, J. Kavalieros
Abstract
For the first time, we report a short channel high performance, gate-all-around strained Si <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.4</inf> Ge <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.6</inf> nanosheet PMOSFET with aggressively scaled dimensions. We demonstrate realization of s-Si <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.4</inf> Ge <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.6</inf> nanosheet with 5nm thickness and device with L <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</inf> =25nm featuring record high I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</inf> =508 µA/µm at I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</inf> =100nA/µm and V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</inf> = -0.5V. This result is obtained with the combination of (a) novel Si-cap-free gate oxide solution featuring thin EOT=9.1A, low D <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IT</inf> and N <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IT</inf> for s-Si <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.4</inf> Ge <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.6</inf> channel, (b) record high hole mobility= 450 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vs owing to compressive strain imparted by Si <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.7</inf> Ge <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.3</inf> strain relaxed buffer (SRB), (c) low R <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">EXT</inf> =150 Ω-µm due to highly active, strained source/drain SiGe process and novel p++ cap layer, (d) optimized source/drain tip and junction to minimize GIDL impact to I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</inf> . Additionally, the impact of operating temperature on GIDL and I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</inf> is comprehensively studied to prescribe optimal V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CC</inf> range of operation for this technology.