11.2 A 26.5625-to-106.25Gb/s XSR SerDes with 1.55pJ/b Efficiency in 7nm CMOS
Ravi Shivnaraine, Marcus van Ierssel, K. Farzan, Dominic DiClemente, G. Ng, Nanyan Wang, Javid Musayev, Gairik Dutta, Masumi Shibata, Arash Moradi, H. Vahedi, Manavi Farzad, Prabhnoor Kainth, Matt Yu, Nhat Nguyen, Jennifer Pham, Angus McLaren
Abstract
The increasing connectivity of devices in our daily lives has driven the need for higher bandwidth in network and data centers. Recently, we have seen the development of 112Gb/s SerDes, particularly for long-reach interfaces [1- 3]. In high-density switch ASICs, we see an increasing demand to improve both area efficiency (mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /lane) and signaling efficiencies (pJ/b) [1- 6]. In a switch ASIC, keeping the SerDes power low translates into broader system power savings since additional power and cost for cooling can be limited or even avoided entirely. One path forward to achieve these important system gains is co-packaged optics (CPO) with an extra-short-reach (XSR) interface. In these applications the switch ASIC and optical engine are no more than 50mm apart which represents a total loss of approximately 10dB at 106.25Gb/s.