Cryogenic Analysis of Junctionless Nanowire MOSFET during Underlap in Lower Technology Nodes
Tenneti Sai Sasank, Pochiraju Raja Ganesh, Nukala Pavan Kumar, Biswajit Jena, Ahmed J. Obaid
Abstract
Abstract This paper presents a cryogenic analysis of Junction less Under lapped Nanowire MOSFETs in lower technology nodes. The temperature dependent analysis is carried out to extract the DC figure of merits (FOMs) of the proposed nanowire MOSFET. The analysis is carried out to investigate the drain current associated with the device at different temperature. Further the analysis is extended with underlap length variation from source, drain and both sides. As the trans conductance plays a vital role in device performance estimation, so the analysis is further extended to calculate the transconductance for all the temperature variation and underlap length variation. With the introduction of gate metal under lapping, the sub-threshold behaviour of the proposed structure under different temperature is carried out extensively.