Characterization of Stable 12T SRAM with Improved Critical Charge
Ashish Sachdeva, V. K. Tomar
Abstract
With the aggressive growth of the internet of things-based applications in the domestic and industrial domain, the embedded static memory is also under renovation stage to eliminate classical barriers such as soft errors, poor stability, and mediocre performance. In this work, a novel twelve transistors (12T) SRAM cell is presented that replaces the conventional inverter with Schmitt trigger-based inverter in core latch. The proposed SRAM circuit has been compared with four formerly reported designs for investigating the improvement in terms of various performance metrics. These designs include conventional six transistors (6T), tunable transistor 8T (T8T), PPN inverter-based 10T (PP10T), and stable low read power 11T (S11T) cells. The presented cell effectively minimizes the soft errors attributed to [Formula: see text]/[Formula: see text]/[Formula: see text]/[Formula: see text] enhancement of critical charge compared to 6T/T8T/PP10T/S11T cells. Also, the proposed bit-cell effectively mitigates multi-bit-cell upsets because it allows bit interleaving array structure. The presented bit-cell also shows reduction in leakage power by [Formula: see text]/[Formula: see text]/[Formula: see text]/[Formula: see text] in comparison to 6T/T8T/PP10T/S11T cells, respectively. The read and write stability of proposed bit-cell circuit is enhanced by [Formula: see text]/[Formula: see text]/[Formula: see text]/[Formula: see text] and [Formula: see text]/[Formula: see text]/[Formula: see text]/[Formula: see text], respectively, in comparison to 6T/T8T/PP10T/S11T cells, respectively. In addition to this, proposed cell exhibits improvement in dynamic power, data retention voltage, and overall electrical quality matrix. Variability comparison of key design metrics such as read power and read current of the proposed SRAM circuit with 6T cell has also been presented in this work.