Subtractor circuits using different wire crossing techniques in quantum-dot cellular automata
Marshal Raj, Suhaib Ahmed, G. Lakshminarayanan
Abstract
The existing CMOS technology is facing severe challenges to keep up with the complicated needs of nanoscale devices due to several issues such as leakage current at nanoscale levels. Quantum-dot cellular automata has the ability to become an alternative to CMOS technology. In general, adder and subtractor are implemented as a single hardware, at the cost of a small reduction in the speed of addition and subtraction. A dedicated hardware for subtractor will reduce the circuit complexity and increase the speed of the operation. Four different subtractor circuit designs are proposed in quantum-dot cellular automata using different wire crossings and implementation techniques. Wire crossing count is critical in determining the cost of the circuit. The proposed multilayer crossover subtractor circuit has 12% fewer cells, 50% wire crossing reduction, and 10% area reduction compared to the existing design. The proposed rotated cell crossover subtractor circuit has 24% fewer cells, 33% clock phase reduction, 50% wire crossing reduction, and 40% area reduction compared to the existing design. Two clock zone crossover subtractor circuit designs are also proposed with smaller area and crossings. The proposed designs can be stretched to construct different N-bit subtractors. The proposed circuit designs are validated using coherence vector engine in QCADesigner.