Integration Design and Process of 3-D Heterogeneous 6T SRAM with Double Layer Transferred Ge/2Si CFET and IGZO Pass Gates for 42% Reduced Cell Size
Xueqiang Yu, M.-H. Chuang, S. W. Chang, W.-H. Chang, Tian-Yu Hong, C.-H. Chiang, Wen-Hsiang Lu, C.-Y. Yang, W.-J. Chen, Jian-Hong Lin, P.-H. Wu, T.-C. Sun, Sekhar Reddy Kola, Yuh‐Shyong Yang, Yun Da, P.-J. Sung, C.-T. Wu, Taemin Cho, G.-L. Luo, Kuo-Hsing Kao, Meng‐Hsueh Chiang, W. C.-Y., C.-J. Su, T.-S. Chao, T. Maeda, Seiji Samukawa, Yiming Li, Y.-J. Lee, W.-F. Wu, Jenn‐Hwan Tarng, Y.-H. Wang
Abstract
In this work, we propose an advanced 3-D heterogeneous 6T SRAM with a newly designed hetero-integration method. CFET inverters and IGZO pass gates are vertically stacked within a 2T footprint area. The Low-Temperature Hetero-Layers Bonding Technique (LT-HBT) process is utilized successfully to fabricate single crystalline heterogeneous Double Layer Transferred (DLT) Ge/2Si CFET-OI on an 8-inch full wafer. Furthermore, an IGZO nFET is deposited and treated as a pass gate (PG) to realize a 6T SRAM operation. The hetero-integration of IGZO PG and self-align DLT Ge/2Si CFET inverters showed improved Read Static Noise Margin (RSNM) and stand-by leakage power. The state-of-the-art 3-D heterogeneous 6T SRAM leads to 42% area reduction.