Litcius/Paper detail

A 0.5-V BLE Transceiver With a 1.9-mW RX Achieving −96.4-dBm Sensitivity and −27-dBm Tolerance for Intermodulation From Interferers at 6- and 12-MHz Offsets

Masahisa Tamura, Hideyuki Takano, Hironori Nakahara, Hiroaki Fujita, Naoya Arisaka, Satoru Shinke, Norihito Suzuki, Yutaka Nakada, Yusuke Shinohe, Shinichirou Etou, T. Fujiwara, Fumitaka Kondo, K. Yamamoto, Tomohiro Matsumoto, Yasushi Katayama

2020IEEE Journal of Solid-State Circuits24 citationsDOI

Abstract

This article presents a 0.5-V RF transceiver fully compliant with Bluetooth low energy (BLE) standards. The receiver (RX) fabricated in a 22-nm fully depleted silicon on insulator (FD-SOI) process achieves a sensitivity of -96.4 dBm, an intermodulation tolerance of -27 dBm for interferers at 6- and 12-MHz offsets, while consuming 1.9 mW. An RX-chain with a gain-programmable low-noise transconductance amplifier (LNTA) provides good linearity over a wide input power range. The LNTA changes amplifier topology according to the gain setting. It achieves a gain range of 41 dB and the IIP3 of -13 dBm at maximum gain. The proposed asynchronous SAR-ADC-based time-to-digital converter (TDC) for the all-digital phase-locked loop (ADPLL) is suitable for low-voltage operation and low-power consumption. It achieves a differential nonlinearity (DNL) of ±0.62 LSB and an integral nonlinearity (INL) of ±0.63 LSB.

Topics & Concepts

IntermodulationDifferential nonlinearityAmplifierdBmLinearityTransceiverIntegral nonlinearityElectrical engineeringSensitivity (control systems)TransconductanceElectronic engineeringNoise figurePhysicsVoltageEngineeringCMOSConvertersTransistorAdvancements in PLL and VCO TechnologiesRadio Frequency Integrated Circuit DesignAnalog and Mixed-Signal Circuit Design