A 1V 32.1 dBm 92-to-102GHz Power Amplifier with a Scalable 128-to-1 Power Combiner Achieving 15% Peak PAE in a 65nm Bulk CMOS Process
Wei Zhu, Jiawen Wang, Ruitao Wang, J. Andrew Zhang, Chenguang Li, Sen Yin, Yan Wang
Abstract
The sixth-generation (6G) wireless communication is emerging and continuous the increase of the speed and data-rate achieved by 5G. A major challenge in 6G is to provide a large transmitter output power (Pout) with high energy efficiency and linearity from a limited supply voltage to overcome high path loss, given the inevitable exploitation of higher millimeter-wave (mm-wave) frequencies (W-band and above) [1]–[5]. The low breakdown voltage of silicon-based processes limits the use of “vertical” power-boost techniques, such as using higher voltages and stacking more transistors. Therefore, the “horizontal” on-chip power-combine technique has attracted more attention. Due to the poor passive efficiency and the physical implementation difficulty, power-combine techniques suitable for high mm-wave systems are scarce. Most of the PAs adopt zero-degree power-combine technique at W-band [3]–[5]. However, the nature of the proportional impedance-transformation ratio with the power combining typically limits the number of combined unit PAs to less than 16 [3]–[5], so that the resulting Pout is generally less than 20dBm.