Litcius/Paper detail

A 1.02-pJ/b 20.83-Gb/s/Wire USR Transceiver Using CNRZ-5 in 16-nm FinFET

Armin Tajalli, Mani Bastani Parizi, Dario Albino Carnelli, Chen Cao, Kiarash Gharibdoust, Davide Gorret, Amit Kumar Gupta, Christopher Hall, Ahmed H. Hassanin, Klaas L. Hofstra, Brian Holden, Ali Hormati, John Keay, Yohann Mogentale, Victor Perrin, J.A. Phillips, Sumathi Raparthy, Amin Shokrollahi, D. Stauffer, R. S. Simpson, Andrew Stewart, Giuseppe Surace, Omid Talebi Amiri, Emanuele Truffa, Anton Tschank, Roger Ulrich, Christoph Walter, Anant Singh

2020IEEE Journal of Solid-State Circuits43 citationsDOI

Abstract

An energy-efficient (1.02 pJ/b) and high-speed (20.83 Gb/s/wire, 417 Gb/s/mm) link for ultra-short reach (USR) applications (up to 6-dB channel loss at the Nyquist frequency of 12.5 GHz) is presented. Correlated non-return to zero (CNRZ) signaling with low sensitivity to inter-symbol interference (ISI) has been developed to improve the link budget. In addition to high pin efficiency (5b6w: 5 bits over 6 wires), the proposed signaling method provides very good resistance against common-mode and crosstalk noise sources, allowing for dense routing. A very wide-band (1.3 GHz) jitter tracking mechanism has been employed to reduce the sensitivity of the system to random and deterministic jitter and relax design constraints on transmitter. A slicer with low kick-back noise and a circuit topology well matched to the continuous-time linear equalizer (CTLE) has been designed to provide both high input sensitivity and Process, supply Voltage, and Temperature (PVT) variations tolerance. The link operates with more than 22-ps (42.5% UI) eye opening at BER = 1E-15. Calibration loops are running in background for quadrature mismatch error correction, clock and data alignment (CDA), and offset removal.

Topics & Concepts

JitterTransceiverTransmitterElectronic engineeringSensitivity (control systems)LinearityPhysicsComputer scienceTopology (electrical circuits)Electrical engineeringEngineeringWirelessChannel (broadcasting)TelecommunicationsAdvancements in PLL and VCO TechnologiesRadio Frequency Integrated Circuit DesignVLSI and Analog Circuit Testing