DTCO Launches Moore’s Law Over the Feature Scaling Wall
Victor Moroz, Xi–Wei Lin, P. Asenov, D. Sherlekar, Minkeun Choi, L. Sponton, Lawrence S. Melvin, J. Lee, Baolian Cheng, A. Nannipieri, Ju Huang, S. Jones
Abstract
Instead of marching from one crisply defined technology node to the next with an uncertain timeline, industry is transitioning toward annual technology updates driven by a schedule, but with an uncertain transistor density increase. Full node updates are expected every other year, with "half-node" updates in between. Pitch scaling began slowing after the 10nm node and is expected to practically cease by the 1nm node. Despite that, transistor density is expected to continue increasing at a similar pace of 45% density increase per node (or 20% per year) through the 1nm node, fueled by increasingly sophisticated Design-Technology Co-Optimization (DTCO) and Electronic Design Automation (EDA) advances.