A Novel Chiplet Integration Architecture Employing Pillar-Suspended Bridge with Polymer Fine-Via Interconnect
Yasuhiro Morikawa, Meiten Koh, Hiroyuki Hashimoto, Chuantong Chen, Ye Wang, Ichiro Kono, Shinji Wakisaka, Ken Ukawa, Takafumi Fukushima, Katsuaki Suganuma, Yoichiro Kurita
Abstract
We proposed a novel chiplet integration technology based on a new bridge architecture, which we call “Pillar-Suspended Bridge (PSB)”, for a wide range of applications including High-Performance Computing (HPC), those that require huge computing power for AI/Metaverse, mobile, and automotive. The technology enables one to connect directly between chiplets/bridges with simplest scheme and does not require a high-cost interposer and realizes “Integrated Circuit of the Integrated Circuits (MetaIC)”. In this paper, we describe the concept and experimental results of the manufacturing of PSB architecture and investigate the key technology to employing high-performance bridge with polymer RDL and dry-etched fine vias.