ASAP5: A predictive PDK for the 5 nm node
Vinay Vashishtha, Lawrence T. Clark
Abstract
We present a predictive process design kit (PDK) for the 5 nm technology node, the ASAP5 PDK. ASAP5 is not related to a particular foundry and the assumptions are derived from literature. It incorporates several innovations that the semiconductor industry has adopted to address scaling challenges, improve reliability and performance. These include contact over active gate (COG), fully self-aligned vias (FSAVs), single diffusion breaks (SDBs), and cobalt interconnects. We discuss implications of these changes in the context of standard cell and static random access (SRAM) bit cells. Interconnect modelling is improved and incorporates the effects of metal fill and barrier geometry on line resistivity. Different metal fill and barrier configurations are compared to determine the PDK interconnect stack. We discuss design rule assumptions for the key layers. The PDK uses horizontal nanowire field-effect transistors (NWFETs) for better ON and OFF-state performance. The transistor compact models are calibrated to the 3-D technology computer-aided design (TCAD) simulation results.