17.6 A 21.7-to-26.5GHz Charge-Sharing Locking Quadrature PLL with Implicit Digital Frequency-Tracking Loop Achieving 75fs Jitter and −250dB FoM
Yizhe Hu, Xi Chen, Teerachot Siriburanon, Jianglin Du, Zhong Gao, Vivek Govindaraj, Anding Zhu, Robert Bogdan Staszewski
Abstract
Sub-sampling (SS) and injection-locking (IL) techniques are becoming increasingly popular for 5G millimeter-wave (mmW) frequency generation [1], [2] due to their ability to achieve ultra-low jitter (<; 100fs). However, as indicated in Fig. 17.6.1 (top-left), sub-sampling PLLs (SS-PLL) typically suffer from high-power consumption, especially in mmW VCO buffers, which isolate the VCO from its sampler for reducing reference spurs, and in the high-speed dividers [2]-[4]. Also, the analog loop filter usually occupies large area. On the other hand, the IL technique for mmW frequency generation requires power-hungry high-frequency injection (~GHz) to fully suppress the oscillator phase noise [1], [4] and cannot ensure robustness over PVT (process, voltage, temperature) [4], which requires an additional frequency-tracking loop (FTL), see Fig. 17.6.1 (top-right). Furthermore, there exists a significant danger of a timing-race problem between the injection reference and FTL, since the frequency error may be corrected by IL before the FTL senses it. In [1], the FTL based on a phase averaging technique can solve the timing-race problem but requires a QVCO and an analog loop filter with relatively large area.