High PAE CMOS Power Amplifier With 44.4% FBW Using Superimposed Dual-Band Configuration and DGS Inductors
Omar Z. Alngar, Adel Barakat, Ramesh K. Pokharel
Abstract
A two-stage 180-nm CMOS wideband (14–22 GHz) power amplifier (PA) with a superimposed staggered technique and defected-ground-structure (DGS) inductors is introduced, where a wideband peaking main stage is designed at the center frequency; then, a superimposed dual-band (SDB) driver stage is proposed to obtain the optimally flat gain response over the whole bandwidth (BW). Also, DGS inductors are used to enhance the power added efficiency (PAE) of the implemented PA by decreasing the matching circuits’ insertion losses. The proposed PA achieved a power gain of 12 dB at a total chip area of 0.564 mm2. Also, at the center frequency, it achieved a saturated output power of 16.6 dBm exhibiting the smallest reported amplitude-to-phase (AM-PM) distortion (2.1°) and group delay (GD) variations (±66 ps). Finally, it gives among the highest fractional bandwidth (FBW) (44.4%) and the PAE (18.7%) so far. Also, it achieves an error vector magnitude of −25 dB at 9.3-dBm output power for a 400-MHz 5G-NR signal.