Vertical Inner Gate Transistors for 4F<sup>2</sup> DRAM Cell
Kyung Kyu Min, Sungmin Hwang, Jong‐Ho Lee, Byung‐Gook Park
Abstract
In this article, we propose a novel cell transistor structure to facilitate the mass production of 4F <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> dynamic random access memory (DRAM). 3-D TCAD simulation results show that the proposed structure exhibits a better DRAM operation margin than the conventional vertical transistors. In particular, we confirmed that the failure mode due to the secondary effect of the floating body, the most pressing issue in relation to 4F <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> DRAM, is dramatically improved by adopting this structure.
Topics & Concepts
DramTransistorDynamic random-access memoryMargin (machine learning)Computer scienceElectrical engineeringOptoelectronicsMaterials sciencePhysicsTopology (electrical circuits)EngineeringSemiconductor memoryVoltageMachine learningSemiconductor materials and devicesAdvancements in Semiconductor Devices and Circuit DesignAdvanced Data Storage Technologies