An mm-Wave Scalable PLL-Coupled Array for Phased-Array Applications in 65-nm CMOS
Hamidreza Afzal, Razieh Abedi, Rouzbeh Kananizadeh, Payam Heydari, Omeed Momeni
Abstract
A new two-element phase-locked loop (PLL)-coupled array for the implementation of millimeter-wave (mm-wave) and subterahertz (sub-THz) phased arrays is presented. This architecture avoids using lossy phase shifter to create the required phase shift between the adjacent elements in a phased-array system. The required phase shift is generated by utilizing a dual nested loop PLL. The two PLL loops work together to stabilize the frequency and create the required phase shift. Moreover, it can be scaled simply by adding more unit cells to the architecture. A 112-121-GHz two-element phased array is designed and fabricated in a standard 65-nm CMOS process. It consumes 147-mW power and provides a phase shift of 46.7° ranging from 58.53° to 105.2° at 117 GHz.