A 12-GHz Calibration-Free All-Digital PLL for FMCW Signal Generation With 78 MHz/μs Chirp Slope and High Chirp Linearity
Zhengkun Shen, Haoyun Jiang, Heyi Li, Zherui Zhang, Fan Yang, Junhua Liu, Huailin Liao
Abstract
A novel all-digital phase-locked loop (ADPLL) for fast and high-linear FMCW signal generation is presented in this paper. Fast chirp slope is enabled by two-point modulation (TPM) technique and ramp linearity distortion induced by digitally- controlled oscillator (DCO) is suppressed by wide loop bandwidth. A calibration-free retiming fractional frequency dividing (FFD) scheme based on digital phase interpolator (DPI) is proposed to suppress the ΔΣ quantization noise and break the loop bandwidth limitation. A parasitic insensitive DPI is utilized in the retiming FFD scheme to achieve high-linear phase interpolation. A high frequency resolution DCO with 9.8-kHz/bit least significant bit (LSB) and a vernier time-to-digital convertor (TDC) with 2.3-ps time resolution are employed to further minimize the quantization noise. Implemented in 40-nm CMOS, the ADPLL prototype consumes 33.8 mW power and 0.32 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> chip area. Measurement results show that 78 MHzμs maximum chirp slope is achieved with 167 kHz root-mean-square (RMS) frequency error. The minimum RMS frequency error is only 5.6 kHz when 300 MHz frequency is swept in 1 ms. The phase noise from 12.15 GHz carrier is -113.6 dBc/Hz at 1-MHz offset.