Energy-Efficient Approximate Multiplier Design With Lesser Error Rate Using the Probability-Based Approximate 4:2 Compressor
L. Hemanth Krishna, Ayesha Sk, J Bhaskara Rao, Sreehari Veeramachaneni, Noor Mahammad Sk
Abstract
This paper proposes novel approximate 4:2 compressors developed using input reordering circuits and input combination probabilities. The input reordering circuit is used to reduce the hardware complexity of the proposed designs. This paper proposes two designs of approximate 4:2 compressors. This compressor is used in designing an approximate multiplier. The proposed multiplier designs utilize less energy than the already published ones due to acceptable inaccurate output/precision, which are best suitable for image processing applications. The proposed multiplier designs MUL1, MUL2, MUL3 and MUL4 saves 22.75%, 21.95%, 11.57%, and 8.95% energy than the best of the existing design 1.