A Fast Half Adder using 8T SRAM for Computation-in-Memory
Jaehyeon Han, Young‐Min Kim
Abstract
The conventional Von Neumann computing architecture faces limitation as data intensive applications have increased. To solve the problem, the new computing platform “computation-in-memory” has been introduced. In this study, a new design of the half adder implemented in memory array using 8T static random-access memory (SRAM) and latch-type sense amplifier is proposed. This design uses four logic gates to implement a half adder. It reduces time delay of getting the final value by 33% compared to the former architecture of the half adder which uses five logic gates.
Topics & Concepts
AdderComputer scienceStatic random-access memoryParallel computingComputationRandom access memoryArithmeticComputer hardwareAlgorithmMathematicsLatency (audio)TelecommunicationsAdvanced Memory and Neural ComputingQuantum-Dot Cellular AutomataFerroelectric and Negative Capacitance Devices