ADC-DSP-Based 10-to-112-Gb/s Multi-Standard Receiver in 7-nm FinFET
Haidang Lin, Charlie Boecker, Masum Hossain, Shankar Tangirala, Roxanne Vu, Socrates D. Vamvakos, Eric Groen, Simon Li, Prashant Choudhary, Nanyan Wang, Masumi Shibata, Hossein Taghavi, Marcus van Ierssel, AdilHussain Maniyar, Adam Wodkowski, Kulwant Brar, Nhat Nguyen, Shaishav Desai
Abstract
This article describes a 4 × 112 Gb/s digital receiver targeting long-reach (LR) channels. An SNR optimized approach is presented, which relaxes the ADC resolution requirement and the number of FFE taps without sacrificing BER. The discrete-time front end overcomes gain-BW limitations to provide 10+ dB gain at 28 GHz. A 56-GS/s ADC then converts the signal to 6-b digital consuming only 195 mW. The following DFE-FFE-based digital equalizer is capable of compensating 36-dB loss achieving a BER of 2e-5. Furthermore, TDC and ISI filter-based low-latency timing recovery meet jitter tolerance specs over a wide range of data rates from 10 to 112 Gb/s, including 28-Gb/s NRZ. The overall receiver consumes 338 mW with 3.18-pJ/bit energy efficiency.