Continuous-Time Incremental Delta-Sigma Modulators With FIR Feedback

Shanthi Pavan, Tanmay Halder, Anand Kannan

2021IEEE Transactions on Circuits and Systems I Regular Papers14 citationsDOI

Abstract

Incremental delta-sigma data converters are useful in applications where one ADC is needed to digitize multiple channels. They can be realized using single- or multi-bit feedback. In both cases, the use of FIR feedback is beneficial in terms of improving the modulator's linearity, reducing the quantizer's complexity, and mitigating the effects of clock jitter (in a continuous-time realization). In the incremental mode, however, the maximum stable amplitude of the ADC is severely impacted by FIR feedback. The reasons behind this are examined, and techniques that mitigate this problem are given. Circuit simulations of an example fourth-order single-bit incremental modulator with an eight-tap FIR DAC are given to illustrate the efficacy of the theory.

Topics & Concepts

JitterDelta-sigma modulationLinearityComputer scienceRealization (probability)ConvertersFeedback loopControl theory (sociology)Modulation (music)Electronic engineeringMathematicsCMOSEngineeringPhysicsElectrical engineeringTelecommunicationsVoltageArtificial intelligenceAcousticsControl (management)StatisticsComputer securityAnalog and Mixed-Signal Circuit DesignAdvancements in PLL and VCO TechnologiesAdvancements in Semiconductor Devices and Circuit Design