Normally-off sputtered-MoS<sub>2</sub> nMISFETs with TiN top-gate electrode all defined by optical lithography for chip-level integration
Kentaro Matsuura, Masaya Hamada, Takuya Hamada, Haruki Tanigawa, Takuro Sakamoto, Atsushi Hori, Iriya Muneta, Takamasa Kawanago, Kuniyuki Kakushima, Kazuo Tsutsui, Atsushi Ogura, Hitoshi Wakabayashi
Abstract
Abstract We demonstrate chip-level integrated n -type metal–insulator–semiconductor field effect transistors with a sputtered molybdenum disulfide (MoS 2 ) thin channel and titanium nitride top-gate electrode, all defined by optical lithography. The devices successfully exhibit a normally-off operation and the highest off-voltage. This is achieved by the single dielectric layer and forming gas annealing, which reduce the positive fixed charges in aluminum oxide (Al 2 O 3 ) film and interface trap densities between the MoS 2 and Al 2 O 3 films, respectively. These normally-off MISFETs are suitable for internet-of-things edge devices with low energy consumption using two-dimensional materials in the future.