An Energy Efficient Low Power CNTFET Implementation of Pseudo-NMOS Based 4:2 Compressor
Chandan Kumar, S. Kavitha, N. Muthukumaran, S. S. Sivaraju
Abstract
In VLSI circuits and systems, a compressor is a crucial digital component which is mainly used in variety of applications such as Digital Signal Processors (DSP), Arithmetic and Logic Units (ALU), etc., A 4:2 compressor contains 4 inputs and 2 outputs to reduce the number of computing stages which leads in reduction of the propagation delay and improving the overall performance of the circuits. Hence, the paper focuses on the design of 4:2 compressor with power reduction mechanism. In VLSI circuits, power reduction approach plays a vital role to enhance the efficiency of the circuits. Here, Pseudo NMOS logic is employed to achieve minimum amount of static power consumption by entirely eliminating the pull up network and is replaced by a single PMOS transistor with ground gated input. Due to this, the pull down network can be easily accessed and able to achieve low static power consumption. The proposed Pseudo-NMOS 4:2 compressor’s performance is validated by comparing it with existing XOR-NOR, Full adder and Transmission Gates based 4:2 compressors in various aspects. The entire implementation is carried out using the HSPICE platform, where parameters such as I<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">avg</inf>, P<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">avg</inf>, E<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">avg</inf>, delay, PDP (Power Delay Product), and EDP (Energy Delay Product) are calculated for both CMOS and CNTFET devices with multiple W/L ratios.