Scaling the SOT track – A path towards maximizing efficiency in SOT-MRAM
S. Van Beek, Kaiming Cai, Faisal Mohd-Yasin, Hubert Hody, Giacomo Talmelli, V.D. Nguyen, Nathali Franchina Vergel, Alvaro Palomino, A. Trovato, Kurt Wostyn, Siddharth Rao, Gouri Sankar Kar, Sébastien Couet
Abstract
We demonstrate, for the first time, the functionality of a scaled perpendicular spin-orbit torque (SOT)-MRAM where the SOT layer and magnetic tunnel junction (MTJ) pillar exhibit comparable dimensions. This novel design leads to a significant reduction in the power consumption (63% decrease), an enhancement in endurance (>10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">15</sup> cycles), and a reduction in bit-cell area. Systematic investigations on device scaling are performed, highlighting the importance of SOT track scaling as a path to enhance the device performance by eliminating power consumption outside the MTJ pillar region. Furthermore, the hybrid free layer stack design offers a potential solution for scaling MTJ dimensions, as it enables low switching current and sufficient retention down to 20 nm.