SRAM-Based Computing-in-Memory Macro With Fully Parallel One-Step Multibit Computation
Edward Choi, Injun Choi, Chanhee Jeon, Gichan Yun, Donghyeon Yi, Sohmyung Ha, Ik‐Joon Chang, Minkyu Je
Abstract
In this letter, we present a multi-bit SRAM computing-in-memory (CIM) macro with enhanced energy efficiency for edge devices tasking machine learning (ML) deep neural networks (DNN). The proposed CIM macro computes matrix-vector multiplications (MVM) in an efficient “one-step" method reducing the energy consumption and control complexity. Furthermore, the proposed method computes not only the multiplications of a single weight but also the multi-bit weight with bit-shifting in the charge domain without the use of additional CMOS switches, thereby achieving very high energy efficiency. Measurement results in a 65-nm CMOS prototype chip show that it achieves the highest throughput of 204.8 GOPS at 1.2V and 133.6 TOPS/W at 0.85V.