Heterogeneous Integration Enabled by the State-of-the-Art 3DIC and CMOS Technologies: Design, Cost, and Modeling
Xi–Wei Lin, Victor Moroz, Xiaopeng Xu, Yankun Gao, Dion Rennie, P. Asenov, Søren Smidstrup, D. Sherlekar, Z. Qin, T. Fang, J. Lee, Minkeun Choi, S. Jones
Abstract
Heterogeneous integration (HI) opens up a new dimension to improve system-level functionality, performance, power, form factor, and cost. Both 3DIC interconnect and monolithic CMOS technology affect the HI strategy and cost, as well as die-to-die data interface design. A novel 3D package, with a 2nm SOC die copper-bonded on an RDL interposer, is analyzed for power integrity and thermal, mechanical, and electrical properties to illustrate co-optimization by modeling.
Topics & Concepts
InterposerInterconnectionCMOSDie (integrated circuit)Power integrityDimension (graph theory)Integrated circuit designThree-dimensional integrated circuitInterface (matter)Computer scienceElectronic engineeringIntegrated circuitEngineeringElectrical engineeringMaterials scienceTelecommunicationsSignal integrityParallel computingOperating systemNanotechnologyMathematicsMaximum bubble pressure methodBubbleLayer (electronics)Etching (microfabrication)Pure mathematics3D IC and TSV technologiesSemiconductor materials and devicesElectronic Packaging and Soldering Technologies