A Residue-Current-Locked Hybrid Low-Dropout Regulator Supporting Ultralow Dropout of Sub-50 mV With Fast Settling Time Below 10 ns
Young‐Ha Hwang, Jonghyun Oh, Woo‐Seok Choi, Deog‐Kyoon Jeong, Jun-Eun Park
Abstract
This article proposes a fully integrated hybrid low-dropout regulator (HLDO) that features an ultralow dropout and a highly improved transient response. This HLDO incorporates a residue-current-locked loop (RLL) that realizes joint regulation using a residue-compensating analog LDO (RLDO) and residue-triggered asynchronous digital LDO (DLDO). The RLDO supplements the residual current to compensate for the current quantization error (CQE) of the DLDO, thus eliminating the limit cycle oscillation (LCO) and improving the power supply rejection compared to standalone DLDOs. Moreover, the RLDO uses a bounded residue control (BRC) scheme that achieves sub-50-mV dropout regulation based on the RLL. The RLDO based on a flipped-voltage-follower (FVF) is equipped with a droop-edge injection scheme, and it improves the fast transient response against a heavy load by promptly triggering the self-clocked DLDO. Residue-driven DLDO control is realized using asynchronous pointer-shift registers (PoSRs) so that the DLDO can respond rapidly without the use of any high-frequency clock. The prototype implemented using a 65-nm CMOS process achieves a 76-mV voltage droop and an 8.2-ns settling time against a load current step of 80 mA/0.5 ns with a 20-mV dropout voltage. The prototype demonstrates load regulation of 0.06 and less than 0.01 mV/mA with a dropout voltage of 20 and 50 mV, respectively, at a 1-V input.